Electronic systems often comprise many individual integrated circuit chips packaged together in a multiple integrated circuit chip module. Multiple-chip module assembly methods include a test known as integrated circuit chip burn-in testing. Burn-in testing includes operating the integrated circuits at a higher than normal operating temperature and voltage to overstress the chips. These tests assure that integrated circuits being tested can satisfy normal operating conditions for which they are designed.
Multiple-chip modules have leads that permit easy electrical connection to the individual chips. At one time, integrated circuit chips were often more expensive than the packaging to which they were attached in forming multiple chip modules. Furthermore, earlier multi-chip integrated circuit modules had fewer chips per module. As a result, it made sense to first assemble integrated circuit chips to the multiple-chip module packaging and then test the individual chips. If a chip failed, the entire module would be discarded. The combined cost and difficulty of testing and perhaps having to discard the entire multiple-chip module, however, was usually less than that of testing and perhaps having to discard the smaller individual chips.
Today's more sophisticated and complicated integrated circuits and packaging technologies have significantly changed cost considerations for integrated circuit module fabrication. With more expensive packaging for complicated integrated circuit modules, as well as reduced integrated circuit fabrication costs, in many cases a significantly larger portion of total fabrication costs go to the packages supporting integrated circuit chips. For complicated circuits and their supporting packaging, it no longer makes economic sense to discard the entire multiple-chip module in the event of a failed integrated circuit chip.
Consequently, there is a need for a device and method that permits integrated circuit chip testing prior to assembly into a multiple-chip integrated circuit module.
Some attempts have been made to overcome limitations associated with test devices that can only test integrated circuits after packaging. For example, U.S. Pat. application Ser. No. 330,839, filed Mar. 30, 1989, entitled "Flip Chip Test Socket Adapter and Method" by S. Malhi, et al., incorporated by reference herein, describes a test socket adapter. That application discloses a method and apparatus for allowing bare chips, i.e., integrated circuit chips prior to packaging, to be tested for burn-in testing. In the Malhi test socket adapter, a bare integrated circuit chip may be inserted into and held. Cantilever beams on the Malhi device deflect and compensate for planarity variations at electrical connections when the chip engages the test socket adapter. The deflection of the cantilever beams allows a positive contact between the test connections and the cantilever beams for burn-in testing.
While the Malhi disclosure solves numerous problems associated with integrated circuit chip testing, significant improvement in such devices is yet necessary. In particular, the cantilever beam structure can only accommodate an integrated circuit chip having a line array of landing pads or solder bumps. That is, only if the integrated circuit test connections surround the perimeter of integrated circuit chip can the cantilever beam structure test the integrated circuit chip. While numerous integrated circuit chips have such a configuration, more complex high performance integrated circuit chips use test connections interior to the perimeter of integrated circuit chip. Additionally, the mechanical structure and materials of the cantilever beams allows no greater separation between the beams than approximately 100 microns. These two problems limit the complexity or, similarly, the test connection density (i.e., number of test connections per unit area) that the test socket adapter can accommodate. Furthermore, the cantilever beams are brittle and can be deflected no more than approximately 50 microns without breaking. This imposes a limit on the planarity differences that can exist between the integrated circuit chip and the adapter.
Thus, there is a need for an integrated circuit chip socket adapter that can provide test connections interior to the perimeter of the integrated circuit chip.
There is also a need for a bare integrated circuit chip test socket that can provide greater test connection density than known devices.
Additionally, there is a need for a bare integrated circuit chip burn-in test socket that provides sufficient compliance for greater planarity differences than conventional adapters provide.